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freescale semiconductor data sheet document number: mcf5475ec rev. 4, 12/2007 ? freescale semiconductor, inc., 2007. all rights reserved. mcf547x tepbga?388 27 mm x 27 mm features list: ? coldfire v4e core ? limited superscalar v4 coldfire processor core ? up to 266 mhz peak internal core frequency (410 mips [dhrystone 2.1] @ 266 mhz) ? harvard architecture ? 32-kbyte instruction cache ? 32-kbyte data cache ? memory management unit (mmu) ? separate, 32-entry, fully- associative instruction and data translation lookahead buffers ? floating point unit (fpu) ? double-precision conforms to iee-754 standard ? eight floating point registers ? internal master bus (xlb) arbiter ? high performance split address and data transactions ? support for various parking modes ? 32-bit double data rate (ddr) synchronous dram (sdram) controller ? 66?133 mhz operation ? supports ddr and sdr dram ? built-in initialization and refresh ? up to four chip selects enab ling up to one gb of external memory ? version 2.2 peripheral comp onent interconnect (pci) bus ? 32-bit target and initiator operation ? support for up to five external pci masters ? 33?66 mhz operation with pci bus to xlb divider ratios of 1:1, 1:2, and 1:4 ? flexible multi-function external bus (flexbus) ? provides a glueless interface to boot flash/rom, sram, and peripheral devices ? up to six chip selects ? 33 ? 66 mhz operation ? communications i/o subsystem ? intelligent 16 channel dma controller ? up to two 10/100 mbps fast ethernet controllers (fecs) each with separate 2-kbyte receive and transmit fifos ? universal serial bus (usb) version 2.0 device controller ? support for one control and six programmable endpoints, interrupt, bulk, or isochronous ? 4-kbytes of shared endpoint fifo ram and 1 kbyte of endpoint descriptor ram ? integrated physical layer interface ? up to four programmable seri al controllers (pscs) each with separate 512-byte recei ve and transmit fifos for uart, usart, modem, codec, and irda 1.1 interfaces ?i 2 c peripheral interface ? dma serial peripheral interface (dspi) ? optional cryptogra phy accelerator module ? execution units for: ? des/3des block cipher ? aes block cipher ? rc4 stream cipher ? md5/sha-1/sha-256/hmac hashing ? random number generator ? 32-kbyte system sram ? arbitration mechanism shares bandwidth between internal bus masters ? system integration unit (siu) ? interrupt controller ? watchdog timer ? two 32-bit slice timers alarm and interrupt generation ? up to four 32-bit general- purpose timers, compare, and pwm capability ? gpio ports multiplexed with peripheral pins ? debug and test features ? coldfire background debug mode (bdm) port ? jtag/ ieee 1149.1 test access port ? pll and clock generator ? 30 to 66.67 mhz input frequency range ? operating voltages ? 1.5v internal logic ? 2.5v ddr sdram bus i/o ? 3.3v pci, flexbus, and all other i/o ? estimated power consumption ? less than 1.5w (388 pbga) mcf547x coldfire ? microprocessor supports mcf5470, mcf5471, mcf5472, mcf5473, mcf5474, and mcf5475
mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 2 table of contents 1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 operating temperatures . . . . . . . . . . . . . . . . . . . . . . . . .4 2.2 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4 hardware design considerations . . . . . . . . . . . . . . . . . . . . . . .6 4.1 pll power filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4.2 supply voltage sequencing and separation cautions . .6 4.3 general usb layout guidelines . . . . . . . . . . . . . . . . . . .8 4.4 usb power filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5 output driver capability and loading. . . . . . . . . . . . . . . . . . .10 6 pll timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7 reset timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . .12 8 flexbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 8.1 flexbus ac timing characteristics. . . . . . . . . . . . . . . .13 9 sdram bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 9.1 sdr sdram ac timing characteristics . . . . . . . . . . .15 9.2 ddr sdram ac timing characteristics . . . . . . . . . . .18 10 pci bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 11 fast ethernet ac timing specifications . . . . . . . . . . . . . . . . .22 11.1 mii/7-wire interface timing specs . . . . . . . . . . . . . . .22 11.2 mii transmit signal timing . . . . . . . . . . . . . . . . . . . . . .23 11.3 mii async inputs signal timing (crs, col) . . . . . . . .24 11.4 mii serial management channel timing (mdio,mdc).24 12 general timing specifications . . . . . . . . . . . . . . . . . . . . . . . .25 13 i 2 c input/output timing specifications. . . . . . . . . . . . . . . . . .25 14 jtag and boundary scan timing. . . . . . . . . . . . . . . . . . . . . .26 15 dspi electrical specifications . . . . . . . . . . . . . . . . . . . . . . . .29 16 timer module ac timing specifications . . . . . . . . . . . . . . . . .29 17 case drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 list of figures figure 1. mcf547x block diagram . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. system pll v dd power filter . . . . . . . . . . . . . . . . . . . . 6 figure 3. supply voltage sequencing and separation cautions . 7 figure 4. preferred vbus connections . . . . . . . . . . . . . . . . . . . . 8 figure 5. alternate vbus connections . . . . . . . . . . . . . . . . . . . . 8 figure 6. usb v dd power filter . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. usbrbias connection. . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. input clock timing diagram . . . . . . . . . . . . . . . . . . . . 11 figure 9. clkin, internal bus, and core clock ratios . . . . . . . 11 figure 10.reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11.flexbus read timing . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12.flexbus write timing . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13.sdr write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14.sdr read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15.ddr clock timing diagram . . . . . . . . . . . . . . . . . . . . 18 figure 16.ddr write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17.ddr read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18.pci timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19.mii receive signal timing diagram. . . . . . . . . . . . . . 23 figure 20.mii transmit signal timing diagram . . . . . . . . . . . . . 23 figure 21.mii async inputs timing diagram . . . . . . . . . . . . . . . 24 figure 22.mii serial management channel timing diagram. . . 24 figure 23.i 2 c input/output timings . . . . . . . . . . . . . . . . . . . . . . 26 figure 24.test clock input timing . . . . . . . . . . . . . . . . . . . . . . . 27 figure 25.boundary scan (jtag) timing . . . . . . . . . . . . . . . . . 27 figure 26.test access port timing . . . . . . . . . . . . . . . . . . . . . . 27 figure 27.trst timing debug ac ti ming specifications . . . . . 27 figure 28.real-time trace ac timing . . . . . . . . . . . . . . . . . . . . 28 figure 29.bdm serial port ac timing . . . . . . . . . . . . . . . . . . . . 28 figure 30.dspi timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 31.388-pin bga case outline. . . . . . . . . . . . . . . . . . . . . 31 list of tables table 1. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . 4 table 2. operating temperatures . . . . . . . . . . . . . . . . . . . . . . . . 4 table 3. thermal resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 4. dc electrical specifications. . . . . . . . . . . . . . . . . . . . . . 5 table 5. usb filter circuit values . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. i/o driver capability . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. clock timing specifications. . . . . . . . . . . . . . . . . . . . . 11 table 8. mcf547x divide ratio encodings. . . . . . . . . . . . . . . . 11 table 9. reset timing specifications . . . . . . . . . . . . . . . . . . . . 12 table 10.flexbus ac timing specifications. . . . . . . . . . . . . . . . 13 table 11.sdr timing specifications . . . . . . . . . . . . . . . . . . . . . 16 table 12.ddr clock crossover specifications . . . . . . . . . . . . . 18 table 13.ddr timing specifications . . . . . . . . . . . . . . . . . . . . . 18 table 14.pci timing specifications . . . . . . . . . . . . . . . . . . . . . . 21 table 15.mii receive signal timing . . . . . . . . . . . . . . . . . . . . . . 23 table 16.mii transmit signal timing . . . . . . . . . . . . . . . . . . . . . 23 table 17.mii transmit signal timing . . . . . . . . . . . . . . . . . . . . . 24 table 18.mii serial management channel signal timing . . . . . 24 table 19.general ac timing specifications . . . . . . . . . . . . . . . . 25 table 20.i 2 c input timing specifications between scl and sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 21. i 2 c output timing specifications between scl and sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 22.jtag and boundary scan timing . . . . . . . . . . . . . . . . 26 table 23.debug ac timing specifications . . . . . . . . . . . . . . . . . 28 table 24.dspi modules ac timing specifications. . . . . . . . . . . 29 table 25.timer module ac timing specifications . . . . . . . . . . . 29
mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 3 figure 1. mcf547x block diagram pll ddr sdram memory controller pci i/o interface & ports commbus usb 2.0 phy* perpheral communications i/o interface & ports fec2** psc x 4 i 2 c fec1 usb 2.0 device* interface flexbus controller flexbus interface pci interface & fifos master/slave interface coldfire v4e core slave bus dspi perpheral i/o interface & ports communications i/o subsystem interrupt controller xl bus arbiter system integration unit dma read dma write multi-channel dma master bus interface & fifos slice timers x 2 gp timers x 4 watchdog timer pci 2.2 controller cryptography 32k system sram crypto r/w xl bus read/write xl bus accelerator*** mmu, fpu emac 32k i-cache 32k d-cache
mcf547x coldfire ? microprocessor, rev. 4 maximum ratings freescale semiconductor 4 1 maximum ratings table 1 lists maximum and minimum ratings for supply and operatin g voltages and storage temperat ure. operating outside of these ranges may cause erratic beha vior or damage to the processor. 2 thermal characteristics 2.1 operating temperatures table 2 lists junction and ambien t operating temperatures. 2.2 thermal resistance table 3 lists thermal resistance values. table 1. absolute maximum ratings rating symbol value units external (i/o pads) supply voltage (3.3-v power pins) ev dd ?0.3 to +4.0 v internal logic supply voltage iv dd ?0.5 to +2.0 v memory (i/o pads) supply voltage (2.5-v power pins) sd v dd ?0.3 to +4.0 sdr memory ?0.3 to +2.8 ddr memory v pll supply voltage pll v dd ?0.5 to +2.0 v internal logic supply voltage, input voltage level v in ?0.5 to +3.6 v storage temperature range t stg ?55 to +150 o c table 2. operating temperatures characteristic symbol value units maximum operating junction temperature t j 105 o c maximum operating ambient temperature t amax < 70 1 1 this published maximum operating ambient temperature should be used only as a system design guideline. all device operating parameters are guaranteed only when the junc tion temperature lies within the specified range. o c minimum operating ambient temperature t amin ?0 o c table 3. thermal resistance characteristic symbol value unit 324 pin tepbga ? junction to ambient, natural convection four layer board (2s2p) jma 20?22 1,2 c/w 388 pin tepbga ? junction to ambient, natural convection four layer board (2s2p) jma 19 1 , 2 c/w
dc electrical specifications mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 5 3 dc electrical specifications table 4 lists dc electrical operating temperatures. this table is based on an operating voltage of ev dd = 3.3 v dc 0.3 v dc and iv dd of 1.5 0.07 v dc . junction to ambient (@200 ft/min) four layer board (2s2p) jma 16 1 , 2 c/w junction to board ? jb 11 3 c/w junction to case ? jc 7 4 c/w junction to top of package natural convection jt 2 1 ,5 c/w 1 ja and jt parameters are simulated in accordance with eia/j esd standard 51-2 for natural convection. freescale recommends the use of ja and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rate d specification. system designers should be aware that device junction temperatures can be significantly infl uenced by board layout and surrounding devices. conformance to the device junction temperature specification ca n be verified by physical measurement in the customer?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-6 with the board horizontal. 3 thermal resistance between the die and the printed ci rcuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4 thermal resistance between the die and the case top su rface as measured by the cold plate method (mil spec-883 method 1012.1). 5 thermal characterization parameter indi cating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. table 4. dc electrical specifications characteristic symbol min max units external (i/o pads) operation voltage range ev dd 3.0 3.6 v memory (i/o pads) operation voltage range (ddr memory) sd v dd 2.30 2.70 v internal logic operation voltage range 1 iv dd 1.43 1.58 v pll analog operation voltage range 1 pll v dd 1.43 1.58 v usb oscillator operation voltage range usb_osv dd 3.0 3.6 v usb digital logic operation voltage range usbv dd 3.0 3.6 v usb phy operation voltage range usb_phyv dd 3.0 3.6 v usb oscillator analog operation voltage range usb_oscav dd 1.43 1.58 v usb pll operation voltage range usb_pllv dd 1.43 1.58 v input high voltage sstl 3.3v/2.5v 2 v ih v ref + 0.3 sd v dd + 0.3 v input low voltage sstl 3.3v/2.5v 2 v il v ss - 0.3 v ref - 0.3 v input high voltage 3.3v i/o pins v ih 0.7 x ev dd ev dd + 0.3 v input low voltage 3.3v i/o pins v il v ss - 0.3 0.35 x ev dd v table 3. thermal resistance (continued) characteristic symbol value unit
mcf547x coldfire ? microprocessor, rev. 4 hardware design considerations freescale semiconductor 6 4 hardware design considerations 4.1 pll power filtering to further enhance noise isolation, an external filter is strongly recommended for pll analog v dd pins. the filter shown in figure 2 should be connected between the board v dd and the pll v dd pins. the resistor and capacitors should be placed as close to the dedicated pll v dd pin as possible. figure 2. system pll v dd power filter 4.2 supply voltage sequenci ng and separation cautions figure 3 shows situations in sequencing the i/o v dd (ev dd ), sdram v dd (sd v dd ), pll v dd (pll v dd ), and core v dd (iv dd ). output high voltage i oh = 8 ma, 16 ma,24 ma v oh 2.4 ? v output low voltage i ol = 8 ma, 16 ma,24 ma 5 v ol ?0.5v capacitance 3 , v in =0 v, f=1 mhz c in ?tbdpf input leakage current i in ?1.0 1.0 a 1 iv dd and pll v dd should be at the same voltage. pll v dd should have a filtered input. please see figure 2 for an example circuit. there are three pll v dd inputs. a filter circuit should used on each pll v dd input. 2 this specification is guaranteed by design and is not 100% tested. 3 capacitance c in is periodically sampled rather than 100% tested. table 4. dc electrical specifications (continued) characteristic symbol min max units board v dd 10 0.1 f pll v dd pin 10 f gnd
hardware design considerations mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 7 figure 3. supply voltage sequencing and separation cautions the relationship between sd v dd and ev dd is non-critical during power-u p and power-down sequences. sd v dd (2.5v or 3.3v) and ev dd are specified relative to iv dd . 4.2.1 power up sequence if ev dd /sd v dd are powered up with the iv dd at 0v, the sense circuits in the i/o pa ds cause all pad output drivers connected to the ev dd /sd v dd to be in a high impedance state. there is no limit to how long after ev dd /sd v dd powers up before iv dd must power up. iv dd should not lead the ev dd , sd v dd , or pll v dd by more than 0.4v during power ramp up or there is high current in the internal esd protection diodes. the rise times on the power suppli es should be slower than 1 microsecond to avoid turning on the internal esd protection clamp diodes. the recommended power up sequence is as follows: 1. use 1 microsecond or slower rise time for all supplies. 2. iv dd /pll v dd and ev dd /sd v dd should track up to 0.9v, then separate for the completion of ramps with ev dd /sd v dd going to the higher external voltages. one way to acco mplish this is to use a low drop-out voltage regulator. 4.2.2 power down sequence if iv dd pll v dd are powered down first, sense circuits in the i/o pads cause all output drivers to be in a high impedance state. there is no limit on how long after iv dd and pll v dd power down before ev dd or sd v dd must power down. iv dd should not lag ev dd , sd v dd , or pll v dd going low by more than 0.4v during power down or there is undesired high current in the esd protection diodes. there are no requiremen ts for the fall times of the power supplies. the recommended power down sequence is as follows: 1. drop iv dd /pll v dd to 0v 2. drop ev dd /sd v dd supplies ev dd , sd v dd (3.3v) sd v dd (2.5v) iv dd , pll v dd supplies stable 2 1 3.3v 2.5v 1.5v 0 time notes: ivdd should not exceed evdd or sd vdd by more than 0.4v at any time, including power-up. recommended that ivdd/pll vdd should track evdd/sd vdd up to 0.9v, then separate for completion of ramps. input voltage must not be greater than the supply voltage (evdd, sd vdd, ivdd, or pll vdd) by more than 0.5v at any time, including during power-up. use 1 microsecond or slower rise time for all supplies. 1. 2. 3. 4. dc power supply voltage
mcf547x coldfire ? microprocessor, rev. 4 hardware design considerations freescale semiconductor 8 4.3 general usb layout guidelines 4.3.1 usb d+ and d- high-speed traces 1. high speed clock and the usbd+ and usbd- di fferential pair should be routed first. 2. route usbd+ and usbd- signals on the top layer of the board. 3. the trace width and spacing of the usbd + and usbd- signals should be such th at the differential impedance is 90 . 4. route traces over continuous planes (p ower and ground)?they should not pass over any power/gro und plane slots or anti-etch. when placing connectors, ma ke sure the ground plane clear-outs around each pin have ground continuity between all pins. 5. maintain the parallelism (skew matched) between usbd+ an d usbd-. these traces should be the same overall length. 6. do not route usbd+ and usbd- traces un der oscillators or parallel to clock tr aces and/or data buses. minimize the lengths of high speed signals that run parallel to the usbd+ and usbd- pair. maintain a minimum 50mil spacing to clock signals. 7. keep usbd+ and usbd- traces as short as possible. 8. route usbd+, usbd-, and usbvbus signals with a minimum amou nt of vias and corners. use 45 turns. 9. stubs should be avoided as much as possible. if they ca nnot be avoided, stubs should be no greater than 200mils. 4.3.2 usb vbus traces connecting the usbvbus pin directly to the 5v vbus signal from the usb connector can cause long-term reliability problems in the esd network of the processor. therefore, use of an external voltage divider for vbus is recommended. figure 4 and figure 5 depict possible connecti ons for vbus. point a, marked in each fi gure, is where a 5v version of vbus should connect. point b, marked in each fi gure, is where a 3.3v version of vbus should connect to the usbvbus pin on the device. figure 4. preferred vbus connections figure 5. alternate vbus connections 4.3.3 usb receptacle connections it is recommended to connect the shield and the ground pin of the b usb receptacle for upstream ports to the board ground plane. the ground pin of the a usb receptacles for downstream ports should also be connected to the board ground plane, but industry practice varies widely on the connection of the shie ld of the a usb receptacles to other system grounds. take precautions for control of ground loops between hosts an d self-powered usb devices through the cable shield. 50k 50k mcf547x b (3.3v) a (5v) 8.2k 20k 50k 50k mcf547 x b (3.3v) a (5v) 50k
hardware design considerations mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 9 4.4 usb power filtering to minimize noise, an external filter is required fo r each of the usb power pi ns. the filter shown in figure 6 should be connected between the board ev dd or iv dd and each of the usb v dd pins. ? the resistor and capacitors should be placed as close to the dedicated usb v dd pin as possible. ? a separate filter circuit should be included for each usb v dd pin, a total of five circuits. ? all traces should be as low impedance as possibl e, especially ground pi ns to the ground plane. ? the filter for usb_phyvdd to vss should be connected to the power and ground planes, respectively, not fingers of the planes. ? in addition to keeping the filter compon ents for the usb_pllvdd as close as practical to the body of the processor as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise onto the portion of that supply between the filter and the processor. ? the capacitors for c2 in the table below should be rated x5r or better due to temperature performance. figure 6. usb v dd power filter note in addition to the above filter circuitry, a 0.01 f capacitor is also recommended in parallel with those shown. table 5 lists the resistor values and supply voltages to be used in the circui t for each of the usb v dd pins. table 5. usb filter circuit values usb v dd pin nominal voltage r1 ( )c1 ( f) c2 ( f) usbvdd (bias generator supply) 3.3v 10 10 0.1 usb_phyvdd (main transceiver supply) 3.3v 0 10 0.1 usb_pllvdd (pll supply) 1.5v 10 1 0.1 usb_oscvdd (oscillator supply) 3.3v 0 10 0.1 usb_oscavdd (oscillator analog supply) 1.5v 0 10 0.1 board ev dd /iv dd r1 c2 usb v dd pin c1 gnd
mcf547x coldfire ? microprocessor, rev. 4 output driver capability and loading freescale semiconductor 10 4.4.1 bias resistor the usbrbias resistor should be placed as close to the dedicat ed usb 2.0 pins as possible. the tolerance should be 1%. figure 7. usbrbias connection 5 output driver capability and loading table 6 lists values for drive capability and output loading. table 6. i/o driver capability 1 1 the device?s pads have balanced sink and source current. the drive capability is the same as the sink capability. signal drive capability output load (c l ) sdramc (sdaddr[12:0], sddata[31:0], ras , cas , sddm[3:0], sdwe , sdba[1:0] 24 ma 15 pf sdramc dqs and clocks (sddq s[3:0], sdrdqs, sdclk[1:0], sdclk [1:0], sdcke) 24 ma 15 pf sdramc chip selects (sdcs [3:0]) 24 ma 15 pf flexbus (ad[31:0], fbcs [5:0], ale, r/w , be /bwe [3:0], oe ) 16 ma 30 pf fec (e n mdio, e n mdc, e n txen, e n txd[3:0], e n txer 8 ma 15 pf timer (tout[3:0]) 8 ma 50 pf dack [1:0] 8 ma 30 pf psc (psc n txd[3:0], psc n rts /psc n fsync, 8 ma 30 pf dspi (dspisout, dspics0/ss, dspi cs[2:3], dspics5/pcss) 24 ma 50 pf pci (pciad[31:0], pcibg[4:1], pcibg0/pcireqout, pcidevsel, pcicxbe[3:0], pcifrm, pciperr, pcireset, pciserr, pcistop, pcipar, pcitrdy, pciirdy 16 ma 50 pf i2c (scl, sda) 8 ma 50 pf bdm (pstclk, pstddata[7: 0], dso/tdo, 8 ma 25 pf rsto 8 ma 50 pf 9.1k usbrbias
pll timing specifications mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 11 6 pll timing specifications the specifications in table 7 are for the clkin pin. figure 8. input clock timing diagram table 8 shows the supported pll encodings. figure 9 correlates clkin, internal bus, and core clock frequencies for the 1x?4x multipliers. figure 9. clkin, internal bus, and core clock ratios table 7. clock timing specifications num characteristic min max units c1 cycle time 15.0 40 ns c2 rise time (20% of vdd to 80% of vdd) ? 2 ns c3 fall time (80% of vdd to 20% of vdd) ? 2 ns c4 duty cycle (at 50% of vdd) 40 60 % table 8. mcf547x divide ratio encodings ad[12:8] 1 1 all other values of ad[12:8] are reserved. clock ratio clkin?pci and flexbus frequency range (mhz) internal xlb, sdram bus, and pstclk frequency range (mhz) core frequency range (mhz) 00011 1:2 41.67?66.66 83.33?133.33 166.66?266.66 00101 1:2 25.0?44.42 50.0?88.83 2 2 ddr memories typically have a minimum speed of 83 mhz. some vendors specifiy down to 75 mhz. check with the memory component specifications to verify. 100.0?177.66 01111 1:4 25.0?33.3 100?133.33 200?266.66 clkin c4 c1 c4 c2 c3 25 50 70 80 100 120 140 160 240 260 60 25.0 clkin (mhz) core clock (mhz) 66.66 200.0 50 70 90 110 30 internal clock (mhz) 2x 2x 4x 2x core clock clkin internal clock 25.0 33.33 130 180 200 220 50.0 133.33 100.0 133.33 266.66 266.66 100.0
mcf547x coldfire ? microprocessor, rev. 4 reset timing specifications freescale semiconductor 12 7 reset timing specifications table 9 lists specifications for the reset timing parameters shown in figure 10 figure 10 shows reset timing for the values in table 9 . figure 10. reset timing 8flexbus a multi-function external bu s interface called flexbus is provided on the mcf54 7 2 with basic functiona lity to interface to slave-only devices up to a maximum bus frequency of 66 mhz. it can be directly connected to asynchronous or synchronous devices such as external boot roms, flash memories, gate-array l ogic, or other simple target (slave) devices with little or no additional circuitry. for asynchronous devices, a simple chip-sel ect based interface can be used. the flexbus interface has six general purpose chip-selects (fbcs [5:0]). chip-select fbcs0 can be dedicated to boot rom access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. control signal timing is compatible with common rom / flash memories. table 9. reset timing specifications num characteristic 66 mhz clkin units min max r1 1 1 rsti and flexbus data lines are synchronized internally. setup and hold times must be met only if recognition on a particular clock is required. valid to clkin (setup) 8 ? ns r2 clkin to invalid (hold) 1.0 ? ns r3 rsti to invalid (hold) 1.0 ? ns rsti pulse duration 5 ? clkin cycles clkin r1 r3 r2 r1 rsti mode select flexbus note: mode selects are registered on the rising clock edge before the cycle in which rsti is recognized as being negated.
flexbus mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 13 8.1 flexbus ac timing characteristics the following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock. table 10. flexbus ac timing specifications num characteristic min max unit notes frequency of operation 25 66 mhz 1 1 the frequency of operation is the same as the pci frequency of operation. the mcf547x supports a single external reference clock (clkin). this signal defines the frequency of operation for flexbus and pci. fb1 clock period (clkin) 15.15 40 ns 2 2 max cycle rate is determined by clkin and how the user has the system pll configured. fb2 address, data, and control output valid (ad[31:0], fbcs [5:0], r/w , ale, tsiz[1:0], be /bwe [3:0], oe , and tbst ) ?7.0 ns 3 3 timing for chip selects only applies to the fbcs[5:0] signals. please see section 9.2, ?ddr sdram ac timing characteristics ? for sdcs[3:0] timing. fb3 address, data, and control output hold ((ad[31:0], fbcs [5:0], r/w , ale, tsiz[1:0], be /bwe [3:0], oe , and tbst ) 1? ns 3 , 4 4 the flexbus supports programming an extension of the address hold. please consult the mcf547x specification manual for more information. fb4 data input setup 3.5 ? ns fb5 data input hold 0 ? ns fb6 transfer acknowledge (ta ) input setup 4 ? ns fb7 transfer acknowledge (ta ) input hold 0 ? ns fb8 address output valid (pciad[31:0]) ? 7.0 ns 5 5 these specs are used when the pciad[31:0] signals are configured as 32-bit, non-muxed flexbus address signals. fb9 address output hold (pciad[31:0]) 0 ? ns 5
mcf547x coldfire ? microprocessor, rev. 4 flexbus freescale semiconductor 14 figure 11. flexbus read timing clkin ad[x:0] ad[31:y] r/w ale tsiz[1:0] fbcsn , be /bwen oe ta fb1 a[x:0] fb2 fb3 tsiz[1:0] fb4 fb5 fb6 fb7 data a[31:y]
sdram bus mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 15 figure 12. flexbus write timing 9 sdram bus the sdram controller supports accesses to main sdram memory from any internal master. it supports standard sdram or double data rate (ddr) sdram, but it does not support both at the same time. the sdram controller uses sstl2 and sstl3 i/o drivers. both sstl drive mo des are programmable for class i or class ii drive strength. 9.1 sdr sdram ac timing characteristics the following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock, when operating in sdr mode on write cycles and relative to sd r_dqs on read cycles. the mcf54 7 x sdram controller is a ddr controller that has an sdr mode. because it is desi gned to support ddr, a dqs pulse must be supplied to the mcf54 7 x for each data beat of an sdr read. the mcf54 7 x accomplishes this by asserting a sign al called sdr_dqs during read cycles. care must be taken during board design to adhere to the following guidelines and specs with regard to the sdr_dqs signal and its usage. clkin ad[x:0] ad[31:y] r/w ale tsiz[1:0] fbcsn , be /bwen ta fb1 a[x:0] a[31:y] data fb2 fb3 tsiz[1:0] fb3 fb6 fb7 oe
mcf547x coldfire ? microprocessor, rev. 4 sdram bus freescale semiconductor 16 table 11. sdr timing specifications symbol characteristic min max unit notes frequency of operation 0 133 mhz 1 1 the frequency of operation is 2x or 4x the clkin frequency of operation. the mcf547x supports a single external reference clock (clkin). this signal defines the frequency of operat ion for flexbus and pci, but sdram clock operates at the same frequency as the internal bus clock. please see the pll chapter of the mcf547x reference manual for more information on setting the sdram clock rate. sd1 clock period (t ck )7.5212ns 2 2 sdclk is one sdram clock in (ns). sd2 clock skew (t sk )tbd sd3 pulse width high (t ckh ) 0.45 0.55 sdclk 3 3 pulse width high plus pulse width low cannot exceed min and max clock period. sd4 pulse width low (t ckl ) 0.45 0.55 sdclk 4 4 pulse width high plus pulse width low cannot exceed min and max clock period. sd5 address, cke, cas, ras, we, ba, cs - output valid (t cmv )0.5 sdclk + 1.0ns ns sd6 address, cke, cas, ras, we, ba, cs - output hold (t cmh )2.0 ns sd7 sdrdqs output valid (t dqsov )self timedns 5 5 sdr_dqs is designed to pulse 0.25 clock before the rising edge of the memory clock. this is a guideline only. subtle variation from this guideline is expected. sdr_dqs only pulses during a read cycle and one pulse occurs for each data beat. sd8 sddqs[3:0] input setup relative to sdclk (t dqsis )0.25 sdclk 0.40 sdclk ns 6 6 sdr_dqs is designed to pulse 0.25 clock before the rising edge of the memory clock. this spec is a guideline only. subtle variation from this guideline is expected. sdr_dqs only pulses during a read cycle and one pulse occurs for each data beat. sd9 sddqs[3:0] input hold relative to sdclk (t dqsih ) does not apply. 0.5 sdclk fixed width. 7 7 the sdr_dqs pulse is designed to be 0.5 clock in width. the timing of the rising edge is most important. the falling edge does not affect the memory controller. sd10 data input setup relative to sdclk (reference only) (t dis )0.25 sdclk ns 8 8 because a read cycle in sdr mode uses the dqs circuit within the mcf547x, it is most critic al that the data valid window be centered 1/4 clk after the rising edge of dqs. ensuring that this happens results in successful sdr reads. the input setup spec is provided as guidance. sd11 data input hold relative to sdclk (reference only) (t dih )1.0 ns sd12 data and data mask output valid (t dv )0.75 sdclk +0.500ns ns sd13 data and data mask output hold (t dh )1.5ns
sdram bus mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 17 figure 13. sdr write timing figure 14. sdr read timing sdclk0 sdclk1 sddm sddata sdaddr, sdba[1:0] sd2 cmd row sd2 sd1 sd5 col sd6 wd1 wd2 wd3 wd4 sd13 sd12 sd3 sd4 sdcsn,sdwe, ras, cas sdclk0 sdclk1 sdcsn,sdwe, sddm sddata sdaddr, ras, cas sdba[1:0] sd2 cmd row sd2 sd1 sd5 col wd1 wd2 wd3 wd4 sd10 3/4 mclk sdrqs sddqs delayed sd11 sd8 board delay sd9 board delay sd7 tdqs reference sdclk form memories (measured at output pin) (measured at input pin) sd6 note: data driven from memories relative to delayed memory clock.
mcf547x coldfire ? microprocessor, rev. 4 sdram bus freescale semiconductor 18 9.2 ddr sdram ac timing characteristics when using the ddr sdram controller, the following timing numbers must be followed to properly latch or drive data onto the memory bus. all timing numbers are relative to the four dqs byte lanes. table 12 shows the ddr clock crossover specifications. figure 15. ddr clock timing diagram table 12. ddr clock crossover specifications symbol characteristic min max unit v mp clock output mid-point voltage 1.05 1.45 v v out clock output voltage level ?0.3 sd_vdd + 0.3 v v id clock output differential voltage (peak to peak swing) 0.7 sd_vdd + 0.6 v v ix clock crossing point voltage 1 1 the clock crossover voltage is only guaranteed when using the highest drive strength option for the sdclk[1:0] and sdclk [1:0] signals. 1.05 1.45 v table 13. ddr timi ng specifications symbol characteristic min max unit notes frequency of operation 50 1 133 mhz 2 dd1 clock period (t ck )7.5212ns 3 dd2 pulse width high (t ckh ) 0.45 0.55 sdclk 4 dd3 pulse width low (t ckl ) 0.45 0.55 sdclk 5 dd4 address, sdcke, cas , ras , we , sdba, sdcs ?output valid (t cmv ) ?0.5 sdclk +1.0 ns ns 6 dd5 address, sdcke, cas , ras , we , sdba, sdcs ?output hold (t cmh ) 2.0 ? ns dd6 write command to first dqs latching transition (t dqss ) ? 1.25 sdclk dd7 data and data mask output setup (dq ?> dqs) relative to dqs (ddr write mode) (t qs ) 1.0 ? ns 7 8 dd8 data and data mask output hold (dqs ?> dq) relative to dqs (ddr write mode) (t qh ) 1.0 ? ns 9 dd9 input data skew relative to dqs (input setup) (t is )1ns 10 dd10 input data hold relative to dqs (t ih )0.25 sdclk +0.5ns ?ns 11 dd11 dqs falling edge to sdclk rising (output setup time) (t dss )0.5 ?ns dd12 dqs falling edge from sdclk rising (output hold time) (t dsh )0.5 ? ns sdclk sdclk v ix v mp v ix v id
sdram bus mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 19 dd13 dqs input read preamble width (t rpre ) 0.9 1.1 sdclk dd14 dqs input read postamble width (t rpst ) 0.4 0.6 sdclk dd15 dqs output write preamble width (t wpre )0.25?sdclk dd16 dqs output write postamble width (t wpst ) 0.4 0.6 sdclk 1 ddr memories typically have a minimum speed specification of 83 mhz. check memory component specifications to verify. 2 the frequency of operation is 2x or 4x the clkin frequen cy of operation. the mcf547x supports a single external reference clock (clkin). this signal defines the frequency of operation for flexbus and pci, but sdram clock operates at the same frequency as the internal bus clock. please see t he reset configuration signals description in the ?signal descriptions? chapter within the mcf547x reference manual . 3 sdclk is one memory clock in (ns). 4 pulse width high plus pulse width low cannot exceed max clock period. 5 pulse width high plus pulse width low cannot exceed max clock period. 6 command output valid should be 1/2 the memory bus clock (sdclk) plus some minor adjustments for process, temperature, and voltage variations. 7 this specification relates to the required input setup time of today?s ddr memories. sddata[31:24] is relative to sddqs3, sddata[23:16] is relative to sddqs2, sddata[15:8] is re lative to sddqs1, and sddata[7:0] is relative sddqs0. 8 the first data beat is valid before the first rising edge of sddqs and after the sddqs write preamble. the remaining data beats is valid for each subsequent sddqs edge. 9 this specification relates to the required hold time of today?s ddr memories. sddata[31:24] is relative to sddqs3, sddata[23:16] is relative to sddqs2, sddata[15:8] is re lative to sddqs1, and sddata[7:0] is relative sddqs0. 10 data input skew is derived from each sddqs clock edge. it begins with a sddqs transition and ends when the last data line becomes valid. this input skew must include ddr memo ry output skew and system leve l board skew (due to routing or other factors). 11 data input hold is derived from each sddqs clock edge. it begins with a sddqs transition and ends when the first data line becomes invalid. table 13. ddr timing specifications (continued) symbol characteristic min max unit notes
mcf547x coldfire ? microprocessor, rev. 4 sdram bus freescale semiconductor 20 figure 16. ddr write timing sdclk0 sdclk1 sdcsn ,sdwe , sddm sddata sdaddr, ras , cas sdba[1:0] cmd row dd1 dd5 dd4 col wd1wd2wd3wd4 dd7 sddqs dd8 dd8 dd7 sdclk0 sdclk1 dd3 dd2 dd6
pci bus mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 21 figure 17. ddr read timing 10 pci bus the pci bus on the mcf54 7 x is pci 2.2 compliant. the following timing num bers are mostly from the pci 2.2 spec. please refer to the pci 2.2 spec for a more detailed timing analysis. table 14. pci timing specifications num characteristic min max unit notes frequency of operation 25 66 mhz 1 p1 clock period (t ck ) 15.15 40 ns 2 p2 address, data, and command (33 < pci 66 mhz)?input setup (t is )3.0 ? ns p3 address, data, and command (0 < pci 33 mhz)?input setup (t is )7.0 ? ns p4 address, data, and command (33?66 mhz)?output valid (t dv )?6.0ns 3 p5 address, data, and command (0?33 mhz) - output valid (t dv ) ? 11.0 ns p6 pci signals (0?66 mhz) - output hold (t dh )0?ns 4 sdclk0 sdclk1 sdcsn ,sdwe , sddqs sddata sdaddr, ras , cas sdba[1:0] cmd row dd1 dd5 dd4 wd1 wd2 wd3 wd4 sddqs dd9 sdclk0 sdclk1 dd3 dd2 sddata wd1 wd2 wd3 wd4 dd10 cl=2 cl=2.5 col dqs read preamble dqs read postamble dqs read preamble dqs read postamble
mcf547x coldfire ? microprocessor, rev. 4 fast ethernet ac ti ming specifications freescale semiconductor 22 figure 18. pci timing 11 fast ethernet ac timing specifications 11.1 mii/7-wire interface timing specs the following timing specs are defined at the chip i/o pin and must be translated appropriatel y to arrive at timing specs/constraints for the emac_10_100 i/o signals. the following tim ing specs meet the requirements for mii and 7-wire styl e interfaces for a range of transceiver devices. if thi s interface is to be used with a specific transceiver device th e timing specs may be altered to match that specific transceiver. p7 pci signals (0?66 mhz) - input hold (t ih )0?ns 5 p8 pci req/gnt (33 < pci 66mhz) - output valid (t dv )?6ns 6 p9 pci req/gnt (0 < pci 33mhz) - output valid (t dv ) ? 12 ns p10 pci req/gnt (33 < pci 66mhz) - input setup (t is )?5ns p11 pci req (0 < pci 33mhz) - input setup (t is )12?ns p12 pci gnt (0 < pci 33mhz) - input setup (t is )10?ns 1 please see the reset configuration signals description in the ?signal descriptions? chapter within the mcf547x reference manual . also specific guidelines may need to be followed when operating the system pll below certain frequencies. 2 max cycle rate is determined by clkin and how the user has the system pll configured. 3 all signals defined as pci bused signals. does not include ptp (point-to-point) signals. 4 pci 2.2 spec does not require an output hold time. although the mcf547x may pr ovide a slight amount of hold, it is not required or guaranteed. 5 pci 2.2 spec requires zero input hold. 6 these signals are defined at ptp (point-to-point) in the pci 2.2 spec. table 14. pci timing specifications (continued) num characteristic min max unit notes clkin input setup/hold p1 p4 p6 p2 p7 output valid input valid output valid/hold
fast ethernet ac timing specifications mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 23 figure 19. mii receive signal timing diagram 11.2 mii transmit signal timing figure 20. mii transmit signal timing diagram table 15. mii receive signal timing num characteristic min max unit m1 rxd[3:0], rxdv, rxer to rxclk setup 5 ? ns m2 rxclk to rxd[3:0], rxdv, rxer hold 5 ? ns m3 rxclk pulse width high 35% 65% rxclk period m4 rxclk pulse width low 35% 65% rxclk period table 16. mii transmit signal timing num characteristic min max unit m5 txclk to txd[3:0], txen, txer invalid 0 ? ns m6 txclk to txd[3:0], txen, txer valid ? 25 ns m7 txclk pulse width high 35% 65% txclk period m8 txclk pulse width low 35% 65% txclk period rxclk (input) rxd[3:0] (inputs) rxdv, rxer m3 m4 m1 m2 txclk (input) txd[3:0] (outputs) txen, txer m7 m8 m5 m6
mcf547x coldfire ? microprocessor, rev. 4 fast ethernet ac ti ming specifications freescale semiconductor 24 11.3 mii async inputs signal timing (crs, col) figure 21. mii async inputs timing diagram 11.4 mii serial management channel timing (mdio,mdc) figure 22. mii serial management channel timing diagram table 17. mii transmit signal timing num characteristic min max unit m9 crs, col minimum pulse width 1.5 ? tx_clk period table 18. mii serial management channel signal timing num characteristic min max unit m10 mdc falling edge to mdio output invalid (min prop delay) 0? ns m11 mdc falling edge to mdio output valid (max prop delay) ?25 ns m12 mdio (input) to mdc rising edge setup 10 ? ns m13 mdio (input) to mdc rising edge hold 0 ? ns m14 mdc pulse width high 40% 60% mdc period m15 mdc pulse width low 40% 60% mdc period crs, col m9 mdc (output) m14 mdio (output) mdio (input) m15 m10 m11 m12 m13
general timing specifications mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 25 12 general timing specifications table 19 lists timing specifications for the gpio, psc, dreq , dack , and external interrupts. 13 i 2 c input/output timing specifications table 20 lists specifications for the i 2 c input timing parameters shown in figure 23 . table 21 lists specifications for the i 2 c output timing parameters shown in figure 23 . table 19. general ac timing specifications name characteristic min max unit g1 clkin high to signal output valid ? 2 pstclk g2 clkin high to signal invalid (output hold) 0 ? ns g3 signal input pulse width 2 ? pstclk table 20. i 2 c input timing specifications between scl and sda num characteristic min max units i1 start condition hold time 2 ? bus clocks i2 clock low period 8 ? bus clocks i3 scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms i6 clock high time 4 ? bus clocks i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 ? bus clocks i9 stop condition setup time 2 ? bus clocks table 21. i 2 c output timing specifications between scl and sda num characteristic min max units i1 1 start condition hold time 6 ? bus clocks i2 1 clock low period 10 ? bus clocks i3 2 scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) ? ? s i4 1 data hold time 7 ? bus clocks i5 3 scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 3 ns i6 1 clock high time 10 ? bus clocks i7 1 data setup time 2 ? bus clocks i8 1 start condition setup time (for repeated start condition only) 20 ? bus clocks i9 1 stop condition setup time 10 ? bus clocks
mcf547x coldfire ? microprocessor, rev. 4 jtag and boundary scan timing freescale semiconductor 26 figure 23 shows timing for the values in table 20 and table 21 . figure 23. i 2 c input/output timings 14 jtag and boundary scan timing 1 output numbers depend on the value programme d into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta b l e 2 1 . the i 2 c interface is designed to scale the actual data tr ansition time to move it to the middle of the scl low period. the actual position is affected by the prescale and division values programmed into the ifdr; however, the numbers given in ta bl e 2 1 are minimum values. 2 because scl and sda are open-collector-type outp uts, which the processor can only actively drive low, the time scl or sda take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 specified at a nominal 50-pf load. table 22. jtag and boundary scan timing num characteristics 1 1 mtmod is expected to be a static signal. henc e, it is not associated with any timing symbol min max unit j1 tclk frequency of operation f jcyc dc 10 mhz j2 tclk cycle period t jcyc 2?t ck j3 tclk clock pulse width t jcw 15.15 ? ns j4 tclk rise and fall times t jcrf 0.0 3.0 ns j5 boundary scan input data setup time to tclk rise t bsdst 5.0 ? ns j6 boundary scan input data hold time after tclk rise t bsdht 24.0 ? ns j7 tclk low to boundary scan output data valid t bsdv 0.0 15.0 ns j8 tclk low to boundary scan output high z t bsdz 0.0 15.0 ns j9 tms, tdi input data setup time to tclk rise t tapbst 5.0 ? ns j10 tms, tdi input data ho ld time after tclk rise t tapbht 10.0 ? ns j11 tclk low to tdo data valid t tdodv 0.0 20.0 ns j12 tclk low to tdo high z t tdodz 0.0 15.0 ns j13 trst assert time t trstat 100.0 ? ns j14 trst setup time (negation) to tclk high t trstst 10.0 ? ns scl i2 i6 i1 i4 i5 i7 i8 i3 i9 sda
jtag and boundary scan timing mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 27 figure 24. test clock input timing figure 25. boundary scan (jtag) timing figure 26. test access port timing figure 27. trst timing debug ac timing specifications tclk (input) j2 j3 j3 j4 j4 v ih v il output data valid tclk data inputs data outputs data outputs data outputs 5 6 input data valid 7 output data valid 8 7 v ih v il output data valid tclk tdi, tms, bkpt tdo tdo tdo 9 10 input data valid 11 output data valid 12 11 v ih v il tclk trst 14 13
mcf547x coldfire ? microprocessor, rev. 4 jtag and boundary scan timing freescale semiconductor 28 table 23 lists specifications for the debug ac timing parameters shown in figure 29 . figure 28 shows real-time trace ti ming for the values in table 23 . figure 28. real-time trace ac timing figure 29 shows bdm serial port ac timing for the values in table 23 . figure 29. bdm serial port ac timing table 23. debug ac timing specifications num characteristic 66 mhz units min max d1 pstddata to pstclk setup 4.5 ? ns d2 pstclk to pstddata hold 4.5 ? ns d3 dsi-to-dsclk setup 1 ? pstclks d4 1 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of clkout. dsclk-to-dso hold 4 ? pstclks d5 dsclk cycle time 5 ? pstclks pstclk pstddata[7:0] d1 d2 past current dsclk dsi dso next current d5 d3 d4
dspi electrical specifications mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 29 15 dspi electrical specifications table 24 lists dspi timings. the values in table 24 correspond to figure 30 . figure 30. dspi timing 16 timer module ac timing specifications table 25 lists timer module ac timings. table 24. dspi modules ac timing specifications name characteristic min max unit ds1 dspi_cs[3:0] to dspi_clk 1 tck 510 tck ns ds2 dspi_clk high to dspi_dout valid. ? 12 ns ds3 dspi_clk high to dspi_dout invalid. (output hold) 2 ? ns ds4 dspi_din to dspi_clk (input setup) 10 ? ns ds5 dspi_din to dspi_clk (input hold) 10 ? ns table 25. timer module ac timing specifications name characteristic 0?66 mhz unit min max t1 tin0 / tin1 / tin2 / tin3 cycle time 3 ? pstclk t2 tin0 / tin1 / tin2 / tin3 pulse width 1 ? pstclk dspi_cs[3:0] dspi_clk dspi_dout dspi_din ds5 ds4 ds1 ds2 ds3
mcf547x coldfire ? microprocessor, rev. 4 case drawing freescale semiconductor 30 17 case drawing
case drawing mcf547x coldfire ? microprocessor, rev. 4 freescale semiconductor 31 figure 31. 388-pin bga case outline
mcf547x coldfire ? microprocessor, rev. 4 revision history freescale semiconductor 32 18 revision history revision number date substantive changes 2.2 august 29, 2005 ta bl e 7 : changed c1 maximum spec from 33.3 ns to 40 ns. 2.3 august 30, 2005 ta bl e 2 2 : changed j11 maximum from 15 ns to 20 ns. 2.4 december 14, 2005 ta bl e 1 0 : changed fb1 maximum from 33.33 ns to 40 ns. ta bl e 1 4 : changed fb1 maximum from 33.33 ns to 40 ns. 3 february 20, 2007 ta bl e 4 : updated dc electrical specifications, v il and v ih . ta bl e 6 : changed flexbus output load from 20pf to 30pf. added section 4.3, ?general usb layout guidelines .? 4 december 4, 2007 figure 2 : changed resistor value from 10w to 10 figure 3 : changed note 1 in from ?ivdd should not exceed evdd, sd vdd or pll vdd by more than 0.4v...? to ?ivdd should not exceed evdd or sd vdd by more than 0.4v...? ta bl e 3 : updated thermal information for jma , jb , and jc ta bl e 4 : added input leakage current spec. ta bl e 6 : added footnote regarding pads having balanced source & sink current. ta bl e 9 : added rsti pulse duration spec. added features list, pinout drawing, block diagram, and case outline.
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document number: mcf5475ec rev. 4 12/2007 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2007. all rights reserved.

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